Hi-Speed USB interfacing
USB 2.0 Solutions | Arasan Chip Systems
USB PHY芯片 | 码农家园
Soft Mixed Signal Corporation USB 2.0 PHY IP Cores
USB 2.0 Device Controller for SoC Designs | Cadence IP
Confidently Characterize Validate and Debug Your USB 31 Electrical PHY Designs | Tektronix
Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
USB 2.0 PHY Verification
The Next-Generation Interconnect | Mouser
Difference between USB and ULPI - Electrical Engineering Stack Exchange
USBPHYC internal peripheral - stm32mpu
USB 3.0/2.0 Combo PHY IP for SoC Designs | Cadence IP
USB 2.0 PHY IP core | Arasan Chip Systems
USB 2.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 40LP /LL)
USB Device
Figure 2 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
ASMedia Demos USB 3.2 Gen 2x2 PHY, USB 3.2 Controller Due in 2019
Canovatech - CT20602
USB 3.0 PHY IP Core
Mixed-Signal Verification for USB 2.0 Physical Layer IP
ULPI - Kcchao
Canovatech - CT25201_PHY
Corigine Unveils First Certified SuperSpeed+ USB 3.1 Gen 2 IP with M31 28nm PHY | audioXpress
USB 2.0 Full High Speed Solution | NXP Semiconductors
